Modern integrated circuits have billions of discrete elements (e.g., transistors). Since simultaneous generation of layouts of all discrete elements in the entire integrated circuit (IC) is not possible, the process of IC layout is executed in stages according to the design hierarchy. In the initial stages, layouts of elementary building elements (e.g., transistors and basic cells) are generated. Afterwards, the layouts of the elementary building elements are united in bigger building blocks, such as macrocells (or macros), which are afterwards united in units constituting the IC layout. Every next stage requires not only pacing the layouts of IC building blocks developed in the previous stage according to the floor plan, but generating layouts of additional circuitry and interconnects providing communication of signals between the IC building blocks developed in the previous stage.
In a course of development of central processing units (CPU), their layouts were traditionally partitioned in bottom-level blocks containing fewer than 10,000 standard cells, wherein each bottom-level block is designed independently. This approach is no longer effective for designing of modern CPUs containing billions of transistors because of a need for designing and optimization of large amounts of bottom-level blocks. In order to improve the automation of synthesized blocks in high-performance CPU designs, a new design style is being pursed. Functional units are being flattened and all macros inside are merged into a single large, flat, high-performance block. The resulting entities are called large block synthesis (LBS) blocks. Typical LBS blocks have a number of cells in the rage of 20-500 thousand cells. This big number of cells in the LBS blocks makes their design quite challenging especially of high clock frequency IC operating in the range of 4 GHz and more.